The present invention relates generally to the field of clock and data recovery methods and apparatuses in general, and more particularly to measures to handle a latency of a clock recovery loop.
Clock and data recovery are an important technique to be used on the receiving side of electronic units. It is generally applied to a received high-speed serial data stream, which is transmitted without any reference to a clock signal.
High-speed digital inputs/outputs (IOs) for receiving an incoming data stream are usually based on an analog-to-digital converter sampled by a phase-rotated clock signal. The phase-rotated clock signal is obtained by means of a clock and data recovery mechanism. Analog-to-digital converters, as well as commonly applied subsequent feed-back equalizers, introduce a significant portion of a loop latency for a data item propagating through a clock recovery loop of the clock and data recovery mechanism. This loop latency generally affects the jitter tolerance specifications which are, e.g., for PCI express generation 3 and 4 and are difficult to meet. Thus, there is a general need to minimize a loop latency of the clock recovery loop.
Document US 2012/0328063 A1 describes a method and an apparatus for minimizing a loop latency caused by a demultiplexer and a phase error processor in a clock and data recovery system. By at least partially embedding a phase error processor into the demultiplexer, a portion of the total latency of a clock and data recovery architecture caused by the demultiplexer and the phase error processor can be reduced to less than a sum of the individual operation latencies.
Document U.S. Pat. No. 8,194,792 B2 discloses a clock and data recovery circuit in which a look-ahead technique is employed to produce a low-latency timing adjustment.
Document U.S. Pat. No. 6,873,668 B2 discloses a clock recovery circuit having two phase comparators operating in parallel and feeding a single loop filter. A first recovery section for recovering a clock signal from the known digital feedback control and a second clock recovery section including either analog feed-forward components or feedback components causing a much shorter clock delay are provided. A first feedback loop is configured to detect a first phase difference using the output of the digital filter and a second feedback loop is configured to detect a second phase difference using the output of the analog-digital converter. The gain of the second feedback loop is adaptively controlled. The second phase difference derived from the output of the analog-digital converter can be used to reduce the clock delay caused by the analog-digital converter thus contributing to boosting the gain of the clock recovery loop.
Document US 2013/0251084 A1 discloses a low-jitter clock recovery unit having a first phase detector for measuring the phase difference between a first clock signal from a voltage-controlled oscillator and a data signal. A phase shifter responsive to a control signal based on the phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the voltage-controlled oscillator. The phase-locked loop including the voltage-controlled oscillator filters out jitter.